Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

implementation of the synergistic processor in 65-nm and 90-nm SOI B. Flachs S. Asano S. H. Dhong H. P. Hofstee G. Gervais R. Kim T. Le P. Liu J. Leenstra J. S. Liberty B. Michael H.-J. Oh S. M. Mueller O. Takahashi K. Hirairi A. Kawasumi H. Murakami H. Noro S. Onishi J. Pille J. Silberman S. Yong A. Hatakeyama Y. Watanabe N. Yano D. A. Brokenshire M. Peyravian V. To E. Iwata This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the highperformance computing community. The Cell Broadband Enginee processor contains eight SPEs. The dual-issue, four-way singleinstruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-FO4 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non–static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.